1. Field of the Invention
The present invention relates to a data reading path management architecture for a memory device, particularly of the non-volatile type.
2. Discussion of the Related Art
In a non-volatile memory, it is important to be able to provide architectures that perform data extraction as quickly as possible and in a reductive embodiment.
One of the solutions that is adopted most frequently is to associate a reference bit line with each bit of a word, so as to provide each selection line with a cell whose conductivity characteristics are fully similar to those of a generic virgin matrix cell, and at the same time, repeat the capacitive load of a corresponding bit line.
A drawback of this solution is the fact that it is not possible to repeat, in a simple way, the load of the entire selection path, such as for example a column multiplexer. Furthermore, the two selected cells (the matrix cell and the reference cell) are at a different distance from the same word line, with a consequent possible difference in signal level.
This drawback is lessened by using static sense amplifiers, in which one waits for the steady-state condition to be reached before proceeding with the reading operation. The use of these sense amplifiers, however, results in a waste of time for reading, since it is unable to dynamically lock the timing of the reading operation to the actual conductivity of a memory cell, i.e., to the signal level that is present therein.
On the other hand, the use of dynamic sense amplifiers is heavily penalized by the above mentioned drawback and by the additional inequality of the capacitive-resistive load of the lines. Furthermore, the architectures of conventional memory devices comprise, for redundancy management, redundancy line groups whose reference is constituted by the same reference columns used for the normal lines of the memory matrix. In this manner, the redundancy bit lines are also compared with the corresponding reference lines, but if a bit is defective on a reference line, then the memory device is defective and must be rejected because it is impossible to change the reference, due to the presence of reference columns, one for each word bit of the memory.